Experience with Chisel in designing a scalable, manufacturable cache directory
summary
Implements a synthesizable pipeline cache directory for multi‑CPU coherency using Chisel and generating FIRRTL, verifies with Python UVM over cocotb using both Verilator and Icarus, and targets Skywater 130nm for manufacturability while planning ASAP7 migration (SRAM modeling blocks that). Adds a custom field‑condition and UVM monitor to keep simulations alive ~100 cycles and emit tickle files for GTKWave, finds and helps fix a reproducible Verilator bug.
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chapters (11)
- 0:00Chisel cache directory project
- 1:03Speaker background
- 2:06Design requirements and challenges
- 2:50Chisel design flow and verification
- 4:13Synthesis feasibility and tech choices
- 4:37Code quality and debugging challenges
- 6:01Open source EDA contributions
- 7:03Debugging assertions and waveforms
- 8:09Unsolved challenges and future work
- 9:14Conclusion and tooling impact
- 10:19Q&A
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