A portable area efficient SRAM compiler: a ... job somebody has to do

on YouTube ↗14m

" summary

A portable SRAM compiler targets IHP SG13G2 with planned ports to Sky130 and GF180MCU, produces both single‑port 6T cells (optionally 8T dual‑port) and full compiler views, and bundles documented Python notebooks that reproduce cell read/write, leakage and read‑current simulations. A test tape‑out is finalizing now and a public compiler release for three open PDKs (single and dual port) is planned by year end; generated macros match or slightly beat IHP area, use up to metal‑3 routing, and favor robust S‑R sense amps over bleeding‑edge speed.

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" chapters (10)

1. 0:00SRAM compiler intro
2. 1:04SRAM cell basics
3. 2:32SRAM design trade-offs
4. 4:21First tape-out process
5. 5:42SRAM blocks and decoders
6. 7:29Compiler design variations
7. 8:33Timing and portability
8. 9:18Test chip finalization
9. 9:40Radiation hardening next steps
10. 10:21Q&A

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