~/talk

RISC-V ISA: Understanding Limitations and Methods to Improve Code Density & Performance

Talkat RISC-V Workshop Chennai 2018 · 2018-07-18..07-19· [embedded-and-hardware]
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Examines RISC-V’s instruction set limitations that affect code density and performance, and presents practical methods to mitigate them. Covers concrete techniques and trade-offs for improving generated code size and speed on RISC-V implementations, with examples and proposals from Western Digital engineers.

AI-written summary · about

  1. 0:00Start
  2. 4:06The problem...
  3. 5:05Compressed Instruction distribution comparison.
  4. 7:20Instruction under study
  5. 7:46ISA & Compiler Recommendations
  6. 12:44Inference
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