Clash: Haskell as an HDL
summary
Clash compiles Haskell to Verilog/VHDL and demonstrates that real hardware can be written as pure Haskell: a tiny parametric CPU is implemented (register count and numeric type are type parameters), expressed as a Mealy-machine that executes one instruction per cycle, with pattern-matched instruction enums, undefined values avoided by laziness, and a working REPL simulation that prints the expected arithmetic stream. Current 0.99 features include co-simulation, bidirectional ports, VCD dumps and user-definable bit representations.
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chapters (8)
- 0:00Introduction
- 2:55Instruction Memory
- 5:42Decoder
- 9:16Program Counter
- 10:38Mealy Machine
- 13:06Simulation
- 15:08Console
- 18:08Conclusion
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