Giving Students A Byte of Open-Source: Advancing Hardware Education
summary
Argues SystemVerilog becomes teachable end-to-end using open-source tooling: FuseSoC, Verilator, Yosys, CVA6, Ibex and DigitalJS for interactive netlist schematics. Autograder pipeline runs linting, unit testbenches, synthesis, gate‑level simulation and P&R timing reports in Docker, even producing leaderboards; one student solution hits an unexpected 13 logic cell result. Extracts real transistor layouts from the Sky130 PDK, builds a working flip‑flop visualizer, and publishes tutorials (three videos, Verilator clip >800 views) to close the gap between behavioral Verilog and silicon.
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chapters (8)
- 0:00Introduction and background
- 0:46Challenges in teaching Verilog
- 3:04Automated grading and feedback
- 6:47Visualizing digital synthesis
- 9:35Advanced architecture concepts
- 10:48Transistor-level visualization
- 12:39Conclusion and resources
- 13:33Q&A and closing remarks
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