From an Open-Source ISA to Open-Source HW to Open-Source Silicon
summary
PULP describes a working pipeline from an RISC-V ISA to open RTL IPs to a full chip built with IHP 130 nm open PDK and open-source EDA (yosys and OpenROAD). The group assembles dozens of IPs into platforms (over 400 RISC-V cores across projects), synthesizes with yosys (plus ABC optimizations), and place‑and‑routes with OpenROAD, producing Basilisk (RTL→GDS open) and claiming up to 1.6× area reduction and 3.5× max‑frequency improvement after six months of flow work.
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chapters (11)
- 0:00Open-source hardware research
- 2:07Open-source hardware benefits
- 3:33Open-source RISC-V hardware IPs
- 5:59Industry and academic adoption
- 7:44Fully open-source IC design
- 9:52Open-source EDA tools and school
- 10:15First open-source chip
- 12:46Conclusion and future
- 14:12Q&A: STA and tape-out
- 14:56Q&A: Research focus and EDA
- 16:22Q&A: Process node and memory
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