Towards Cycle-accurate Simulation of xBGAS
summary
Claims a cycle-accurate SST simulator (REV-xBGAS) that models xBGAS by extending the Rave CPU component, adding an extended register file mapped to base RISCV registers and a remote memory controller with four queues. Demonstrates get and broadcast microbenchmarks (2-node and 8-node), emits CSV traces and simulated time, and evaluates network topologies and latencies. Notes prior software overheads of up to 44% for fine-grained remote accesses and shows simulation of large-scale disaggregated-memory scenarios.
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chapters (13)
- 0:00xBGAS project introduction
- 1:46Partitioned Global Address Space
- 3:50Traditional PGAS challenges
- 5:49xBGAS architecture
- 9:58xBGAS runtime library
- 10:59Why SST for simulation
- 12:49RISC-V CPU modification
- 13:53SST simulation workflow
- 14:55Get operation simulation demo
- 15:39Broadcast operation demo
- 16:44Experimental results
- 17:05Summary and future work
- 17:48Q&A
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