pyadi-jif: JESD204 tools for mere mortals
summary
Open-source configuration library pyadi-jiff models clock chips, converters and FPGA constraints, solves mixed-integer PLL/divider equations with CPLEX or Gekko, and emits device-tree and FPGA constraints via pyadi-iio. Demonstrated on ADI hardware (AD9680/AD9144 with a 9523 clock) by changing sample rate from 1 GS/s to 500 MS/s: lane rate becomes 5 Gbps, core clock 125 MHz, device-tree updated, JESD link comes up and GNU Radio shows the expected 40 MHz tone — the workflow works end-to-end.
AI-written summary · about
chapters (7)
- 0:00pyadi-jif and JESD204 intro
- 8:44JESD204 config challenges
- 14:27JIFF and pyadi-jif tools
- 17:55JIFF clock and config fixes
- 20:46JIFF to hardware translation
- 24:58Live demo: GNU Radio & hardware
- 28:08Summary & pyadi-jif resources
related talks
33mDo It Faster: How We Supercharged Linux To Work With Blazing Fast ADCs for IIO
23mCedarEDA for open source silicon
38mOpen-Source Tools for FPGA Development
17mEnabling Precise Timing Control in SDRs
49mFPGA: creating hardware by programming
26mA Clock-Distribution Abstraction for Resource-Constrained Real-Time Systems in Zephyr
32mgr-iio: Nuances, Advanced Features, and New Stuff
20mbsg_pearls: Effortlessly Synthesizable Building Blocks That Work Right Out of the Shell