Adventures in RFNoC: Lessons Learned From Developing a Real-Time Spectrum Sensing Block
summary
Implementation details for an RFNoC FSS block on an Ettus X310: the block uses AXI-Stream Payload Context and Cheddar packets, provides two architectures (single-pass passthrough with a static threshold and a cached-packet version that computes thresholds), exposes a secondary data port for results, and uses mod tool + generate_verilog.py plus imagecore.yaml for synthesis. Measured latencies are one clock cycle data latency and three clock cycles product latency, the system runs at 200 MS/s, and image builds take ~45–90 minutes. Registers increment by 4 bytes.
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chapters (10)
- 0:00Introduction to RFNoC
- 1:15Spectrum sensing overview
- 3:40Data interfaces and flow
- 7:44Designing the FSS architecture
- 11:19Developing the RFNoC block
- 14:44Configuring parameters
- 18:59GNU Radio integration
- 21:12Synthesis and deployment
- 24:19Performance analysis
- 27:06Q&A and closing
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