A Clock-Distribution Abstraction for Resource-Constrained Real-Time Systems in Zephyr
summary
Builds a clock-tree reconfiguration graph from Zephyr device descriptions, measures per-clock execution times with the Platin binary analyzer, and encodes reconfiguration penalties so the scheduler solves a min-cost flow optimization over releases and deadlines. Evaluation on ESP32-C3-style platforms uses randomized workloads and reports ~70% average energy savings versus always-on baselines while preserving timing constraints. Recommends richer device-tree metadata (power per clock source, transition costs) to make the static analysis and optimizations practical.
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chapters (9)
- 0:00Introduction
- 1:37Constrained systems scenarios
- 4:29Energy efficiency challenges
- 7:04Clock tree trade-offs
- 9:20Static analysis for guarantees
- 12:13Reconfiguration graph concept
- 16:48Optimization for energy savings
- 17:59Current status and future
- 20:21Open discussion
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