RISC-V Goes BIG
summary
Andes reports shipping about 3 billion cores last year and holding roughly 250 commercial licenses while offering cores from tiny MCUs up to an eight‑stage RISC‑V 45 series that runs Linux-capable multicore systems with an optional coherence manager and L2 cache. Commercial chips already include a DSP p extension and a vector unit with a streaming port for high‑throughput accelerators, and one core family reaches ISO 26262 ASIL B for automotive use.
AI-written summary · about
chapters (13)
- 0:00Intro
- 0:46RISC-V Powering Industry Leaders
- 3:19RISC-V Deployment - Renesas ASSP RENESAS
- 3:59RISC-V Deployment - PICOCOM OpenRAN Family PC802 • Using 2x Andes N25F x16 clusters - Single issue
- 5:53RISC-V Deployment - Renesas GP MPU
- 6:39RISC-V goes BIG RISC-V is moving up • From small MCU to mid end and on the way to high end Cores
- 8:41Andes Technology Corporation Who We Are
- 11:47Andes Added Value in RISC-V
- 12:16RISC-V DSP Extension (Packed SIMD/DSP)
- 13:01Andes Custom Extension - EDA Tool
- 15:52A(X)45MP: Cache-Coherent Multicore
- 18:34Andes Partners and Ecosystem
- 19:53Andes Wrap up Andes Technology : your Trusted Partner!
related talks
02h 18mRISC-V 101
10mKeynote: Owning Your Silicon Future Starts with Building on RISC-V
19mKeynote: Designing the Next Billion Chips: How RISC-V is Revolutionizing Hardware
17mA dive into RISC-V
09mLightning Talk: RISC-V and AI: How an Open-Standards ISA Underpins Portability f...
24mPorting the Oberon system to the RISC-V instruction set architecture
11mBoosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions
24mOpen Acceleration for RISC-V – Portability, Performance and Partners...