Keynote: Owning Your Silicon Future Starts with Building on RISC-V

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" summary

Tenstorrent releases concrete RISC‑V hardware and software: an open-source Ocelot CPU (BOOM‑based) and a high‑performance Ascalon core on forthcoming developer silicon, a silicon‑proven logic analyzer and trace/debug chain, open verification environments and tools (Spike, riscv‑tooling), plus a stimulus generator with 20,000 tests for ISA compliance. The collateral runs Linux, targets AI/HPC/embedded, and aims to cut CI time by providing downloadable reference platforms and IP so teams can build and validate real, high‑performance RISC‑V systems.

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" chapters (9)

1. 0:00Introduction
2. 1:03Company mission in AI hardware
3. 2:06What is RISC-V
4. 3:31RISC-V needs high-performance hardware
5. 4:13Enabling RISC-V ecosystem
6. 5:36Open-sourcing debug and system IP
7. 7:01RISC-V innovation building blocks
8. 8:25Developer platforms and tools future
9. 9:51Conclusion on open standards

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