The Big-endian RISC-V Linux Adventure
summary
Project implements RISC‑V runtime big‑endian support end‑to‑end: added QEMU (≈120‑line patch) flags and page‑table handling, updated OpenSBI to set per‑hart endian bits, and landed a contained Linux kernel (≈150‑line patch) removing fragile asm, fixing MMIO byte‑order macros and KVM/kvmtool quirks. CVA6 RTL on FPGA gets byte‑swap on load/store, atomics fix via unused bus flag and pipeline fences, and the stack boots OpenSBI → U‑Boot → shell. GCC mostly works (GCC15 fixes an NPTL build crash); patches are published.
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chapters (12)
- 0:00Introduction to endianness in computing
- 1:08Project goals and software stack challenges
- 3:40Modifying QEMU and OpenSBI for big-endian
- 6:08Linux kernel and userland big-endian porting
- 9:18QEMU changes and OpenSBI updates
- 11:47Kernel patching and IO code updates
- 13:13KVM and hypervisor support for big-endian
- 15:44Hardware availability and MIPS collaboration
- 17:10Performance impact of big-endian optimizations
- 19:23Testing with CVA6 on FPGA boards
- 23:18Conclusions challenges and future work
- 25:48Q&A and closing remarks
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