HW-SW Interface for RAS in RISC-V Architectures
summary
A hardware–software RAS interface for RISC-V implements memory error aggregation, logging and escalation with configurable feature and control registers, per-record address and 32-bit timestamp, counters for corrected errors, and prioritised eviction; the prototype uses two error record banks paired with a 4-entry FIFO and 32-bit timestamps. The design is synthesized on standard cells and Xilinx Zynq UltraScale FPGA, validated on an FPGA running 32 RISC-V cores executing ECC-protected programs with error injection, showing area scales with record count and frequency is not a limiter.
AI-written summary · about
chapters (10)
- 0:00Introduction by host
- 1:09About the talk
- 2:16What is RAS in computing
- 5:08Error classification in RAS
- 7:17RAS interface architecture
- 11:56Implementation details
- 12:41Synthesis and FPGA results
- 14:30Validation and testing
- 14:51Conclusion and advantages
- 15:34Q&A and closing remarks
related talks
20mRISC-V open designs and contributions to hardware security research and development activities
06mDemo: RISC-V Dual Lock-step Implementation for Safety and Security Applications
47mA Security RISC? The State of Microarchitectural Attacks on RISC-V
27mControl Flow Integrity on RISC-V
24mSystem Level Security Verification of RISC V Based SoCs
19mOpen-Source Commercial-Grade RISC-V IOMMU with Verification
18mCPU Security in the Context of RISC-V
59mNationally Critical Infrastructure needs Secure Hardware