Enhancing the RISC-V Trace Encoder to Verify the Control-Flow and More
summary
Implements two verifiers: a standard-compliant verifier and an enhanced trace encoder on FPGA around an Ibex RISC‑V core; static tool generates metadata and a standalone memory stores discontinuity addresses and signatures. Enhanced design adds per‑basic‑block and pipeline execution signature model and a shadow stack, reports packets after every discontinuity, and reduces verification latency. Experiments use r332 IMC binaries, simulated fault injections and electromagnetic attacks plus nbench/IOT benchmarks and successfully detect skipped calls and return/address tampering with no software changes.
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chapters (10)
- 0:00Introduction to project
- 1:04Fault injection attacks threat
- 3:13Trace encoder verification idea
- 4:39Architecture and workflow
- 6:24Limitations of initial approach
- 6:44Enhancing trace encoder standard
- 8:09Code and control flow integrity
- 9:14Implementation and results
- 10:38Summary and future work
- 11:39Q&A session
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