Mitigating Transient-Execution Attacks with CHERI Compartments
summary
Reproduces six transient‑execution attacks (four Spectre variants plus two Meltdowns) on an out‑of‑order superscalar CHERI RISC‑V softcore and shows secrets can leak at hundreds of kilobytes per second. Proposes enforcing sealed capabilities and atomic domain transitions so speculation is allowed inside but blocked across compartments, letting capabilities express fine‑grained bounds and permissions. Claims vulnerability depends on microarchitecture not ISA and argues for ISO‑level guarantees that compilers (not programmers) can use to insert compartment transitions; prototype evaluation demonstrates feasibility.
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chapters (8)
- 0:00Introduction to transient execution
- 2:09Transient execution attack mechanics
- 4:21CHERI architecture overview
- 6:27ISA design properties and gaps
- 9:18Architectural guarantees for security
- 10:01CHERI compartmentalization
- 12:08Conclusion and future work
- 12:34Q&A session
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