RISC-V and Antmicro’s visual system designer: Everything everywhere all at once
summary
A visual system designer ties an open-component database, Renode simulator and Kenning + IREE ML toolchain to let users assemble RISC‑V cores, peripherals, SoCs and full boards, generate Renode simulation models and firmware, and run hundreds of binaries in interactive dashboards. The stack already produces KiCad footprints and photorealistic 3D models for dozens of boards, supports co‑development with RTL (used on Microchip PolarFire and OpenTitan), and integrates riscv‑dv verification via the collector project to validate custom vector and ML extensions.
AI-written summary · about
chapters (11)
- 0:00Intro
- 0:59Fragmentation? More like augmentation
- 3:07Always improving the open source landscape, connecting, documenting, filling the blanks
- 4:00Using SW data and structure to test
- 6:37Open source components database with KiCad footprints and Blender models
- 7:16Interactive schematics viewer
- 9:22Unleash the freedom provided by RISC-V
- 10:39Generate Renode simulation files
- 11:27Co-development of ML, vector, custom instructions
- 11:49Gather metrics from your implementation
- 12:20Generate Zephyr firmware, U-Boot, Linux
related talks
11mDemo: Accelerating SW Development and Validation of RISC-V Based Designs
03mRenode - open source systems simulation framework
22mStay Ahead with the Latest Advances in RISC-V Development Tools
10mRISC-V Virtual Platforms for Early RISC-V Embedded Software Development
42mPanel: RISC-V in Education and Training: Successes and Gaps
11mDemo: Catapult Studio for Imagination RISC-V CPUs
20mNext generation IDE for your RISC V Product in 20 Minutes
40mPanel: Toolchains & Runtime