The Future of Security is in Open Silicon

on YouTube ↗45m

" summary

An open RISC-V security CPU hosts a Zephyr-based root of trust that enforces three internal privilege levels, hardware-enforced permissions, and signed C containers tied to per-route keys stored in OTP. The design includes AES/SHA/PK crypto engines, a key-derivation core, a key transport core, and 24 MPU regions for locked memory ranges. A Linux kernel module, a QEMU emulator and a Xilinx Zynq‑7000 FPGA reference exist for integration and CI, and container loading, signature verification and permission checks operate end-to-end.

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" chapters (17)

1. 0:00Intro
2. 2:03Rambus At a Glance
3. 4:01Spectre/Meltdown/Foreshadow
4. 8:07Use Cases
5. 8:40Some brief CMRT terminology
6. 10:50Agenda
7. 11:48CPU/MPU
8. 16:37Crypto Engines
9. 18:22Key Derivation Core
10. 20:13Other important cores
11. 21:43CMRT SW Architecture
12. 22:51First-stage Bootloader
13. 24:31Security Monitor
14. 27:51Supervisor OS/Keme
15. 32:28Building and executing containers
16. 37:51Why Zephyr?
17. 44:10Questions?

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