Empowering the Next Generation of High-Performance, Power-Efficient Servers
summary
Synopsys and Arm describe concrete flows and tools: emulation with Zebu Server 4 runs 24x7 at high MHz to validate Neoverse platforms and prune billions of cycles down to ~100k via Zebu Empower for power-tuning; Fusion Compiler picks glitch-tolerant multipliers and balances routing because wire delay rises (M1 resistance ~4x at N3) and glitches consume 27–30% power in arithmetic-heavy designs; PCIe 6.0 at 64 GT/s and CXL/CpI choices drive connectivity and coherence tradeoffs.
AI-written summary · about
chapters (9)
- 0:00Start
- 2:11Richard Richards
- 3:17What Kind of Hardware Infrastructure Is Required To Validate a Complex Hpc Chip on Arm Neoverse Platforms
- 4:47How Important Is Emulation in this Context
- 8:28Silicon Life Cycle Management
- 19:23How Are Workloads Being Managed from Software Hardware into Power Analysis and Optimization across the Design Flow
- 20:23Max Power Pattern
- 21:55Picking the Right Workload
- 24:24Security
related talks
21mState of ARM-based HPC
16mChange Your Chip Architecture and Save the World
12mArm Neoverse software ecosystem and the open source strategy
16mKeynote: Designing Processors in the Cloud: How Advanced Emulation and AWS Cloud Infrast...
02h 35mChipyard and FireSim End to End Architecture Exploration with RISC V
26mA New Way to Disrupt the Datacenter
06mPOWER your Cloud
36mIBM’s Next Generation POWER Processor and Memory Roadmap