IBM’s Next Generation POWER Processor and Memory Roadmap
summary
Roadmap shows a concrete I/O-first strategy: a 2020 POWER9 advanced-I/O chip with 24 SMT cores, 120 MB L3, eight DDR ports delivering ~150 GB/s sustained, 48 PCIe Gen4 lanes and 25 Gb links; POWER10 in 2021 moves to Samsung 7 nm, PCIe Gen5 and 32/50 Gb signaling plus more memory bandwidth. Design centers on OMI for technology-agnostic buffered DIMMs, openCAPI evolution (v4/v5) for coherent accelerators, and a working prototype low-latency NAND hybrid card (FPGA controller) that targets in-memory DBs and lowers cost.
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chapters (14)
- 0:00Introduction and speakers
- 1:25Audience and talk focus
- 2:31Shift in processor strategy
- 3:56Power 9 IO chip overview
- 6:31Power 9 acceleration features
- 8:21Advanced IO chip details
- 10:50Open CAPI design goals
- 14:23Open CAPI evolution
- 17:39Memory roadmap and OMI
- 21:16OMI benefits and innovation
- 25:32Hybrid memory subsystem
- 26:40Storage class memory
- 30:40Hybrid memory prototype
- 32:30Summary and power 9a IO
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