OpenCAPI BoF - A Memory Centric Fabric for a Data Centric World
summary
OpenCAPI-backed FPGA cards are shown working as hybrid memory subsystems: a PCIe full‑height card with two OpenCAPI links houses DDR4, SRAM, MRAM and up to 3 TB Xenon per card, aiming at 1 µs avg read latency at 20 GB/s after warmup (initial host hits ~5 µs). Power10 and OMI extend that model toward 50–100 ns memory inception latency and OpenCAPI 3.0/4.0 support; RTL and FPGA bring‑up platforms are already available on GitHub for prototyping.
AI-written summary · about
chapters (10)
- 0:00Start
- 1:52Craig Petrie
- 6:29Market Trends
- 7:58Card Specifications
- 22:29What's Next on Power 10 for all Fpga Accelerators
- 25:23Forward Migration Path
- 39:16What's Next for Um Ocxl
- 39:39What's Next for Ocxl
- 49:16Working with Cloud Providers
- 59:54What Is the Power Consumption Comparison of Eight Rmi Channels Compared to a Single on Package Hbm Channel
related talks
36mIBM’s Next Generation POWER Processor and Memory Roadmap
19mEnabling Big Memory workloads to run
39mFunction Dedicated Network Deployment Model in DPU/IPU-Like Device Acro...
18mOctopus: Enhancing CXL Memory Pods via Sparse Topology
06mPOWER your Cloud
14mMultitenancy for Fast and Programmable Networks in the Cloud
06mUsing FPGA's and Xeon processors to accelerate cloud workloads
05mDay 1 Keynote