An Overview of the Self Boot Engine (SBE) in POWER9 base OpenPOWER Systems
summary
Overview of the Self Boot Engine in POWER9: a dedicated PPE42 32-bit core with 96 KB SRAM plus bolt-on peripherals implements on-chip boot, secure root-of-trust via OTP fuses, and chip-op abstractions that hide register details from the BMC. External control uses an 8-entry FIFO (upstream/downstream) over the C-FAM/FSI path and an eight-register PSU mailbox (4 cmd, 4 response) to offload host timers, preserve memory across IPL, capture FFDC debug dumps, and update C‑PROM; firmware is compressed, staged L1/L2 loaders, and sources are open.
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chapters (16)
- 0:00Introduction
- 0:58What is the SBE
- 6:45Hardware Block Diagram
- 12:08FIFO Protocol
- 14:15FIFO Commands
- 18:59Other Interface
- 20:36Commands
- 21:09Deadman Control Loop
- 24:05Firmware Architecture
- 26:13Boot Sequence
- 28:38Boot Flow
- 31:04Secure Hardware Access
- 31:35Linux
- 32:11Announcements
- 33:27Conclusion
- 34:51Glossary
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