OpenCAPI Accel: Unleash the Power of Customized Accelerators
summary
OC-Accel is an OpenCAPI platform that lets FPGA accelerators access host memory coherently in C1 mode, accelerator-initiated transactions. It implements an OpenCAPI→AXI bridge with a 1024-bit (128‑byte) data path, HLS (C++) or Verilog flows, libocxl kernel support, and simulator co‑simulation (Cadence/ModelSim). Measured throughput is about 21.6 GB/s host→FPGA and ~18 GB/s duplex and latency ≈495 ns read / ≈450 ns write at 200 MHz; supports 32 AXI IDs and multiple process contexts.
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chapters (20)
- 0:00Introduction
- 3:06offload CPU computation
- 4:36FPGA
- 6:03OCX
- 8:11Support Package
- 9:08Main Workflow
- 11:05Hardware Development
- 11:56AXI Features
- 16:31Documentation
- 16:59Bandwidth
- 17:48Latency
- 19:01Shared Memory
- 20:05Acceleration Framework
- 21:02Scattered Memory Access
- 22:26Software Hardware Cooperation
- 23:27GPU and FVG
- 24:23Ethernet
- 24:57LoadEMA
- 29:20Data Logs
- 30:12Status Exchange
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