Hybrid Memory Project and OpenCAPI
summary
Claims hybrid DRAM+flash reaches near-DRAM speeds (about 1.1–1.7× slower) using two concrete techniques: an interruptible write for flash that roughly doubles effective performance, and a 16:1 DRAM:flash ratio front-end cache that recovers latency. Built a modular FPGA-based Proteus platform with a Xilinx UltraScale+, four independent DDR4 DIMM controllers, custom DDR4-format flash DIMMs, AXI4 logic, a hybrid tier manager and OpenCAPI links; a demo exists, full benchmark numbers are still in progress.
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