Leveraging the RISC-V Efficient Trace (E-Trace) Standard

on YouTube ↗10m

" summary

Describes a compact encoding that reports start address and only branch outcomes and indirect targets so instruction flow is reconstructed without logging every opcode. Claims bits per instruction drop enough to trace more cores and longer runs and optional features yield about 40% BPI improvement. Covers branch-taken/not-taken encoding, delta-address mode, and an enhanced encoder that adds cycle-accurate trace so timing and targets are observable and bandwidth offchip is reduced.

AI-written summary · about

" chapters (6)

1. 0:00Introduction
2. 0:50Why do we need Trace
3. 2:40How ETrace works
4. 4:52ETrace Standard
5. 7:00ETrace Features
6. 8:22Conclusion

" related talks

• 18mLeveraging the RISC-V Efficient Trace (E-Trace) StandardIain Robertson · RISC-V Summit North America 2023
• 36mRISC V Tracing What is DifferentNino Vidovic · emBO++ 2023
• 16mEfficient debug and trace of RISC-V systems: a hardware/software co-design approachOana Alexandra Lazar, Henrique Mendes, Angelo Maldonado-Liu · RISC-V Summit Europe 2025
• 19mRatified N-Trace Specifications - an OverviewRobert Chyla, Jay Gamoneda · RISC-V Summit North America 2024
• 11mSimulate, trace, and evaluate a RISC-V system leveraging very long vectorsPablo Vizcaino · RISC-V Summit Europe 2024
• 14mRISC-V Debugging: Custom ISA Extensions, Multicore, DTM VariantsMarkus Götzle · 8th RISC-V Workshop Barcelona 2018
• 02h 00mAdvanced Debug and Trace Tools for RISC-V ArchitecturesMaurizio Menegotto · RISC-V Summit Europe 2026 Developer Workshops
• 21mEvery CPU Cycle CountsIain Robertson, Gajinder Panesar · RISC-V Summit 2019