Siemens Interview

on YouTube ↗04m

" summary

Claims a silicon IP that implements the RISC‑V processor branch trace scheme, compresses on‑chip instruction traces enough to support simultaneous multi‑CPU trace with lower off‑chip bandwidth, and ships an enhanced trace encoder plus monitoring IPs that provide non‑intrusive visibility. Also offers an embedded SDK to build self‑contained analytics that run in‑field for real‑time error detection and profiling, aiming to shorten debug time and reduce time‑to‑market.

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" chapters (4)

1. 0:00Introduction
2. 0:23What is Trace
3. 1:28Benefits for customers
4. 2:27Outlook

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