Perf feature improvements in RISCV
summary
RISC-V perf currently relies on esop_pmf and SBI PMU with firmware-provided event-to-counter maps but new ISA extensions add counter delegation allowing S-mode access to counters; patches and a first driver version introduce static-key checks to prefer the ISA path and fall back to SBI. A key implementation detail is event-to-counter mapping for 29 programmable counters, so the proposal puts a counter ID mask into the perf JSON/config2 (making many events raw) and raises compatibility and vendor-encoding concerns that need resolution.
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chapters (9)
- 0:00Introduction to RISC-V perf
- 1:44Counter delegation extension
- 3:09Event to counter mapping issues
- 6:21Backward compatibility plan
- 8:26SBI vs I extension usage
- 10:13Cycle and instruction events
- 12:03Event discovery challenges
- 13:30Counter mapping constraints
- 15:16Vendor-specific encoding
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