Shared FPU Support in Zephyr for ARM64 and RISC-V
summary
Zephyr implements lazy FPU context switching for ARM64 and RISC‑V to avoid saving 512‑byte FPU state on every switch, using a global owner tag and per‑thread FPU save areas; ARM64 gains a trap‑handler instruction emulation for STR Q to avoid gratuitous traps from variadic printf, RISC‑V requires illegal‑instruction decoding to recognize FP ops, and SMP uses IPIs plus a spinlock wait hook to pull remote FPU state. Several corner‑case instruction sets were missing and are now fixed; the implementation runs and reduced unnecessary FPU saves.
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chapters (13)
- 0:00Introduction and background
- 1:06Zephyr and FPU context switching
- 8:41Hardware FPUs and register files
- 9:30Zephyr’s floating point support
- 11:57Lazy FPU context switching
- 16:20Optimizing FPU access
- 18:05FPU usage in exceptions
- 22:04ARM64 variadic arguments surprise
- 25:47RISC-V FPU trap handling
- 29:04SMP and IPI for FPU context
- 30:13Spinlock and FPU contention
- 31:40Source code and Q&A intro
- 32:21Discussion and final Q&A
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