An introduction to the DPLL subsystem
summary
A new Linux 6.7 subsystem exposes DPLL hardware via a netlink API to configure inputs, priorities and pin routing and to monitor lock status, phase offset and chip temperature. It models DPLL devices plus separate pin objects, supports automatic/manual selection, and records per-pin frequency limits. Drivers exist: Meta ocp TP (PPS), NVIDIA mlx5 (SyncE) and Intel ice (multiple DPLs); testing infrastructure is proposed via RFC patches and nedevsim integration.
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chapters (7)
- 0:00Introduction to DPL
- 2:14DPL device operation
- 6:24Pin configuration details
- 7:32DPL API overview
- 9:45Existing driver implementations
- 11:36Testing and collaboration
- 13:04Q&A
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