An API for Cache Stashing Hints
summary
DPDK gets an ethdev-level API proposal that maps application hints into PCIe TLP processing hints so NICs can stash I/O into a chosen CPU cache level. Hardware examples include Intel e810 and Broadcom BCM57500 with steering-tag registers and platform targets like AMD Zen5 and Arm Neoverse N2/V2. Measured behavior shows about 40% performance uplift when stashing to LLC; stashing deeper (L2) is plausible. API work specifies capability discovery per RX/TX queue, set-steering-tag Q context calls, ACPI DSM lookup and the need for kernel support to expose firmware functions (ACPI DSM).
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chapters (8)
- 0:00Introduction to cache stashing
- 1:04What is cache stashing
- 6:37TLP processing hints overview
- 14:04Steering tags in practice
- 18:43Why a stashing hints API
- 22:39API functions and objects
- 27:22Helper functions for steering tags
- 32:48Q&A and future work
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