Lessons Learnt from Reusing QDMA NIC to Base Band PMD
summary
Project reuses AMD Xilinx QDMA NIC PMD as a BBDEV front end and wires RTL LDPC encode/decode engines into a short‑circuited RX/TX path. Early prototype runs at ~15 Gbps and 127 µs round‑trip; after fixes selective SIMD builds, code sectioning into 4K pages, an RT ring + pointer‑swap to avoid memcopies, and DMA tweaks reach ~40–48 Gbps and 33 µs latency. Workarounds include device ID masking and per‑queue scalar/vector handlers; requests: real‑world BBDEV examples and low‑latency DMA benchmarks.
AI-written summary · about
chapters (19)
- 0:00Introduction and context
- 1:02Reusing QDMA NIC for baseband
- 3:51Prototype and round-robin distribution
- 6:22Customer use case and latency issues
- 9:36Profiling and cache misses
- 12:48Lockless implementation with RT rings
- 17:30Lessons learned and optimizations
- 20:19Q&A session begins
- 21:03Performance improvements with optimizations
- 23:36CPU and cache considerations
- 24:46RT rings and software latency
- 27:57Dedicated queues for low latency
- 30:24Buffer management and recycling
- 33:12Inlining and instruction cache bloat
- 34:58Real-world use cases vs benchmarks
- 35:44Hardware and thread locality
- 37:52Threading models in PMDs
- 41:03Abstracting hardware locality
- 42:50Closing remarks and thanks
related talks
23mMulti-Path Transport for RDMA in Datacenters
13mLive in the Express Lane
23mFixing the E310 Bottleneck: Implementing a High-Rate Heterogeneous...
14mUnderstanding RDMA Microarchitecture Resources for Performance Isolation
18mRDMA is Turing complete, we just did not know it yet!
33mBringing packet queueing to XDP
02h 53mPreview Sessions
01h 01mnet_mdev: Fast path user space I/O