Monitoring 400G Traffic in DPDK Using FPGA-Based SmartNIC with RTE Flow
summary
Cesnet builds a 400G FPGA-based SmartNIC around an Intel Agilex 7 on PCIe Gen4/5, implements an FPGA pipeline that processes four frames per clock to mark, filter, drop and export metadata at 400 Gbps, and exposes control via RTE flow. Firmware is an open NDK platform (VHDL components), with a DPDK PMD and an open IPFIX probe plus FlowTest traffic generator. A hardware connection tracking table aggregates long flows and exports records, but that export is not yet expressible with current RTE flow rules.
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chapters (9)
- 0:00Introduction and motivation
- 1:29Monitoring fundamentals
- 2:34Hardware design challenges
- 4:44NDK platform overview
- 6:32DPDK RTE flow limitations
- 8:18400G SmartNIC capabilities
- 9:03Monitoring applications
- 13:25Open source resources
- 13:46Q&A session
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