Enabling Programmable Transport Protocols in High Speed NICs
summary
Paper presents Tonic, a hardware template and API that implements transport logic (segment selection and credit management) constrained to a few kilobits per flow and nanosecond timing. An FPGA-based prototype meets timing for 100 Gbps back-to-back 128-byte packets, generating an address every 10 ns for >1,000 active flows; common per-segment bitmaps and fixed-function modules shrink user code to ~200 lines versus 8,000 lines of NIC glue, and all evaluated protocols meet 100 MHz timing.
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chapters (10)
- 0:00Intro
- 0:24The Transport Layer
- 2:08Constant Innovation in Transport Logic
- 5:04Interfacing with the Rest of the Stack
- 6:18Challenges of Hardware Programming for High-Speed NICS
- 7:43Tonic's Approach
- 8:33Transport Logic in Hardware: First Attempt
- 10:38Decoupling Transport Processing
- 16:01Evaluation - Programmability
- 17:37Summary
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