SoNIC: Precise Realtime Software Access and Control of Wired Networks
summary
SoNIC implements the physical and data‑link layers in software using commodity multi‑core CPUs plus an FPGA transceiver board and PCIe Gen2 DMA (32 Gbps) to generate and capture 10.3125 Gb/s Ethernet bitstreams in real time. It counts idle other characters (12 minimum) to achieve nanosecond precision inter‑packet timing, pins up to five kernel threads per port, validates output against an oscilloscope, produces uniform gaps where hardware tools show variance, and builds a 100 ns timing channel with measured 0.37% BER.
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chapters (14)
- 0:00Start
- 0:28Interpacket Delay and Network Research
- 1:18Network Research enlightened via the PHY
- 3:43Precision + Software Physics equipment???
- 4:54Challenge
- 5:4510GbE Network Stack
- 9:18SONIC Design: Hardware
- 9:52SONIC Design: Software
- 10:57SONIC Design: Synchronization
- 11:51SONIC Design: Optimizations
- 12:51SONIC Design: Interface and Control
- 14:09Packet Generation and Capture
- 15:50Packet Capture
- 16:29Covert Timing Channel
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