Adding RAS Support for CXL Port Devices - Terry Bowman
summary
Adds RAS handling by changing where internal-error callbacks live: a proof-of-concept CXL port service is tried then rejected because it duplicates CXL register mapping and logging; an AER struct extension is tested but remains port-limited; final approach moves internal-error callbacks into the PCI driver with runtime PCI callback registration so any PCIe device (not just CXL) can register handlers. Also lands a special-case for CXL RCH RCRB AER reporting (patches accepted in kernel 6.7).
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chapters (8)
- 0:00Introduction
- 0:22CXL and RAS overview
- 2:05PCIe port bus driver
- 4:14CXL 1.1 downstream port handling
- 6:46CXL 2.0 and future constraints
- 8:55Three solution options for RAS
- 14:19Solution three and requirements
- 18:12Q&A on PCIe and RAS handlers
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