CXL Type-3 device discovery, configuration in firmware and prepare ACPI tables...
summary
Firmware builds ACPI tables so the kernel sees CXL Type‑3 memory as nodes: ACPI HMAT/SRAT/CEDT prepared and per‑host‑bridge CHB objects with UIDs linking host bridges to memory windows. Firmware performs pre‑AP SCP PCIe enumeration and a new CXL DXE during DXE to read CDAT and configure interconnects; kernel validates topology via the existing CXL framework. Work runs on a Neoverse N2 FVP with CXL 2.0 port; current test uses a single root port, single Type‑3 endpoint and demonstrates enumeration but reports that HDM interleaving logic is not yet implemented.
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chapters (9)
- 0:00Introduction and context
- 1:59System objectives
- 3:38Host bridge and firmware
- 4:44CDT and configuration tables
- 6:45Hardware simulation platform
- 9:09System hardware architecture
- 12:23Firmware boot process
- 13:13Enumeration and discovery
- 22:30Q&A and closing remarks
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