Meta’s CXL Journey and Learnings in Linux
summary
Meta reports system-level prototypes that meet latency and power budgets and upstream kernel work including transparent page placement and a user-space profiler. Transparent page placement keeps a tested web-cache workload within ~1% of baseline when 32 GB of 96 GB is CXL memory. Interleave tuning shows default 1:1 can cause ~40% drop while a 5:1 interleave gives ~8% uplift for bandwidth-heavy jobs. Device work covers a CXL driver mailbox, event framework (design on paper), reset/HTM/Hotplug limits and current need for firmware-driven host switching.
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chapters (24)
- 0:00Introduction to CXL journey
- 1:48What is CXL technology
- 3:35CXL protocol versions overview
- 5:46Meta’s CXL system prototyping
- 6:51Memory management goals
- 8:14User space profiling tool
- 8:56Transparent page placement
- 10:02Bandwidth optimization
- 11:29Scale management challenges
- 13:57Event management design
- 16:02CXL reset complications
- 17:47Memory visibility in Linux
- 19:54Proposal for memory reporting
- 21:23Call to action and community
- 22:50Future tuning needs
- 24:40Hot plug and memory sharing
- 25:22Q&A on CXL distance limits
- 27:55Q&A on virtualization and memory
- 29:23Q&A on memory access paths
- 30:04Q&A on memory failure handling
- 31:49Q&A on dynamic memory provisioning
- 32:30Q&A on kernel isolation
- 33:17Performance tuning tools
- 34:44Final Q&A and wrap-up
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