RISC-V ftrace: working with preemption
summary
RISC-V ftrace currently patches a reserved area at each function (usually reserve 16 bytes per function) using a stop-the-world stop_machine approach; enabling preemption exposes partially-updated four-instruction trampolines that corrupt return frames. Proposed work replaces stop_machine with aligned trampolines and atomic stores (needs functions aligned at 4/8 bytes and GCC falign), plus a runtime trampoline allocator; prototype shows roughly ~500KB code growth and requires expensive synchronization like synchronize_rcu_tasks to be safe.
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chapters (15)
- 0:00Introduction to RISC-V ftrace
- 1:06Current ftrace implementation
- 3:14Stop machine limitations
- 6:29Preemption and atomicity issues
- 9:17Alternative solutions explored
- 10:44ARM64 and x86 approaches
- 13:37Prior art and atomicity
- 16:56RISC-V specific challenges
- 18:48PPC-RISK comparison
- 21:15RCU tasks synchronization
- 23:01Breakpoint atomicity debate
- 24:45Hardware vendor coordination
- 26:33Proposed RISC-V solution
- 27:40Troline approach details
- 30:20Code size impact
