Make LL/SC arch has a strict forward guarantee
summary
Claims that LL/SC ISAs lack a strict forward-progress guarantee and that microarchitecture details determine whether loads-reserve/store-conditional succeed. Patches implement an assembly compare-and-exchange path, a combo local implementation merging LL/SC and CAS, and a litmus-style microbenchmark run on real machines from GitHub. Results show one machine observes failures only a few per million, while a weaker implementation shows roughly 100× higher failure rates. Examines ARM’s exclusive monitor and a lock-cache/locked-cache microarchitecture that gives much stronger progress.
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chapters (5)
- 0:00Introduction to LL/SC
- 4:25Atomic instruction categories
- 13:53Forward progress guarantees
- 23:36Microarchitecture implementations
- 29:20Architecture requirements summary
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