New Technologies in the Arm Architecture
summary
Announces two committed Arm architecture features: SVE2 (adds NEON-style DSP/media ops and extra instructions) and TME (hardware transactional memory with transactional lock elision). SVE2 exposes 128–2048-bit scalable vectors with vector-length-agnostic code that matches NEON at 128-bit and yields 40–70% more vectorized dynamic instructions and up to ~5–7× speedups on wider vectors in benchmarks. TME shows real gains (eg memcached ~40% throughput/latency improvement, DPDK cuckoo higher) and GCC/LLVM support targets early 2020; ISA XML posts imminently.
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chapters (8)
- 0:00Introduction to new Arm features
- 1:11Addressing Moore's law limitations
- 6:37Scalable Vector Extension v2 overview
- 13:04Transactional Memory Extension explained
- 27:27SVE2 enhancements and performance
- 33:35TME implementation and benefits
- 44:34Future plans and open-source support
- 49:14Q&A on memory barriers and silicon timing
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