End2End: From Silicon to System Delivery
summary
Marvell delivers ThunderX2 end-to-end: silicon with 8 memory channels per SoC and out‑of‑order cores supporting up to four threads per core, a CRB reference platform with CRB reference platform with Gigabyte and AMI firmware/BMC, plus upstream kernel work 9–12 months before production. HPE’s Apollo 70 and Sandia’s Astra reach Top500, Cadence ports EDA tools with a Flexera licensing wrapper, and customers report improved performance per dollar and memory‑bandwidth wins for HPC and cloud workloads.
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chapters (10)
- 0:00Introduction to end-to-end delivery
- 4:20Marvell’s infrastructure focus
- 10:31Enabling platform and standards
- 12:00HPC use cases with Sandia and Los Alamos
- 15:51Cray and compiler performance
- 17:41Microsoft Azure and OCP integration
- 19:06University of Michigan Big Data cluster
- 21:13Cadence EDA tools on ThunderX2
- 23:45Performance metrics and optimization
- 27:38Call to action for Linaro and ecosystem
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