Design your own custom co-processors and acceleration hardw
summary
Course outlines how to prototype custom accelerators on an Ultra96 board using SDSoC and the PYNQ-like Python framework, with concrete results: a matrix‑multiply accelerator runs ~24x faster at 100 MHz and ~38x at 300 MHz versus CPU, limited by AXI data movement rather than fabric clock. It demonstrates bitstream reloads under a second (SRAM‑based, effectively unlimited), points to Adam Taylor projects, element14 reference designs and hands‑on Ultra96 v2 training.
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chapters (13)
- 0:00Intro
- 1:21Co-Processing History
- 3:37Co-Processors and Acceleration Hardware
- 6:39Programmable Logic - What is it?
- 10:05A REAL Example
- 11:11What is going on behind the curtain?
- 25:00Blogs and Projects
- 27:07Documentation
- 32:05Reference Designs
- 39:05Ultra96-V2 Kit Overview
- 40:01Ultra96-V2 Block Diagram
- 42:42Microchip ATWILC3000 Pre-Certified Countries
- 43:29Ultra96 - Xilinx Programmable Logic Advantage
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