Improvement and enhancement of LLVM for HPC

on YouTube ↗19m

" summary

Describes concrete LLVM changes for HPC: implements a modified register allocation strategy with virtual-register splitting and a virtual-register spill layout, adds a software pipelining pass tuned to AArch64 loop idioms, and extends codegen for the Fujitsu A64FX Scalable Vector Extension target. Reports results on LBM and kernel suites: modified LLVM reduces store instructions and register pressure, yields a 9% end-to-end benchmark win and up to 2× speedup on tight kernels, and exposes remaining backend codegen gaps.

AI-written summary · about

" chapters (5)

1. 0:00Introduction to HPC and LLVM
2. 5:09Fujitsu's scalable vector extensions
3. 10:19Vectorization improvements in LLVM
4. 13:11Benchmarking and performance impact
5. 16:09Conference summary and Q&A

" related talks

• 17mUnlocking 15% More Performance: A Case Study in LLVM Optimization for RISC-VMikhail R. Gadelha · RISC-V Summit North America 2025
• 16mImprovements to RISC-V Vector code generation in LLVMAlex Bradbury, Luke Lau · RISC-V Summit Europe 2025
• 17mRISC-V LLVM State of the UnionAlex Bradbury · RISC-V Summit North America 2024
• 24mRISC V LLVM: Towards A Production-Ready LLVM-Based ToolchainAlex Bradbury · 7th RISC-V Workshop 2017
• 17mMaking LLVM RISC-V Compiler More Performant for EveryoneIvan Baev · RISC-V Summit North America 2023
• 24mGenerating BPF Verifier Friendly Code with ClangYonghong Song · Linux Plumbers Conference 2023
• 15mPushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC...R. Fuhler · RISC-V Summit North America 2025
• 22mReconciling High-level Optimizations and Low-level Code in LLVMJuneyoung Lee · OOPSLA 2018