All Programmable SoCs?
summary
Describes running neural nets on Xilinx UltraScale+ MPSoC using the SDSoC/SDAccel flow and prebuilt libraries, not hand RTL, and shipping a $249 Ultra96 dev board with a one-year SDSoC license. Shows a binary-network pipeline trained on Amazon for $7.78, converted to bitstream and streamed in fabric, yielding about 15,000 fps on the FPGA vs ~94 fps on the CPU (claimed ~8,600× speedup) and emphasizes data-movement pragmas and DMA tuning.
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chapters (10)
- 0:00Introduction to FPGAs
- 1:08Why FPGAs matter now
- 2:51Zynq UltraScale+ MPSoC overview
- 5:22Programming the FPGA fabric
- 8:17High-level synthesis for software
- 10:26Matrix multiply example
- 13:55Machine learning acceleration
- 16:09Ultra96 board launch
- 18:42Binary neural network demo
- 22:19Q&A session
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