Accelerating Neural Networks for Vision Systems via FPGAs
summary
Implements a Binary Neural Network on an FPGA with an embedded processing system, trained on the German traffic sign set (~50,000 images), and deployed on a 96‑board demo that sustains >8,000 images/sec, claiming roughly four orders of magnitude speedup over a software run (about 2.2 images/sec on a CPU). Memory footprint and multiplier cost drop to one‑bit operations, enabling on‑chip weights; reported peak accuracies hit ~97% though some classes fall to ~93%.
AI-written summary · about
chapters (9)
- 0:00Introduction and audience setup
- 1:54Challenges in neural networks
- 8:06Real-time requirements and FPGA benefits
- 11:19Silicon devices overview
- 17:54Programmable logic accelerators
- 23:37Reduced precision neural networks
- 26:49Binary neural network demo
- 28:32Software and OS support
- 29:58Closing and next session
related talks
01h 11mMachine Learning Acceleration in an Embedded World
01h 54mDNNs on FPGAs
01h 52mNeural Network Accelerator Design
13mAccelerating AI algorithms
01h 55mNeural Networks and Accelerator Co-Design
13mAdding A Binarized CNN Accelerator To RISC V For Person Detection
34mBuilding FPGA-based Machine Learning Accelerators in Python
20mComputer Vision at the Edge with OpenVINO