Tuning in-kernel routines on RISC-V
summary
Trying to speed kernel string and memcpy paths on RISC‑V by switching to architecture‑optimized implementations instead of the generic C fallbacks, with patches to expose detection in the CPU device node and a plan for unified discovery of ISA and microarchitectural features. Selection ideas include alternatives code patching or an IFUNC‑like resolver and runtime benchmarking like crypto does, but concerns remain about PC‑relative relocations, per‑hart performance differences and misaligned access emulation breaking some options.
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chapters (13)
- 0:00Introduction to tuning
- 1:24Current kernel string functions
- 3:08Detecting fast string extensions
- 5:59IPA and runtime selection
- 8:25Microarchitecture impact
- 11:12Central role of memcopy
- 13:21Per-core performance issues
- 15:06Alternatives mechanism
- 17:13Vendor extensions and limits
- 19:45Cache and microarchitecture
- 21:08Low-hanging optimizations
- 22:55Dynamic selection challenges
- 24:41Q&A and future steps
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