Integrated PCIe monitoring and tracing facilities
summary
Integrated PCIe monitoring and tracing facilities embed a kisai PMU and a PTT tracer in the SoC PCIe controller to count link events and record TLP headers (4DW or 8DW formats) into DMA buffers with a hardware comparator and minimal overhead. Users access events via sysfs and use perf integration (perf record/report) to capture and decode traces; runtime tuning of link parameters goes through an AMU to prevent corruption. A simple memcpy test shows buffer-allocation counts rise by roughly 600–700 (from ~6,000 to ~6,700) after increasing TX allocation, demonstrating observable, low-cost performance change.
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chapters (13)
- 0:00Introduction to PCIe monitoring
- 1:10Why we need these facilities
- 2:37Introducing PMU and PTT devices
- 3:59Monitoring unit composition
- 5:28Using PMU for monitoring
- 8:59Introducing PTT trace device
- 10:45Using PTT for tracing
- 12:58Trace data formats
- 15:52Hardware implementation details
- 17:47Dynamic link tuning
- 23:27Potential use scenarios
- 26:21Tuning example with PMU and PTT
- 28:53Open questions and feedback
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