Restartable Sequences: Scheduler-Aware Scaling of Memory Use on Many-Core Systems
summary
Patches implement a per-memory-space virtual CPU ID and per-mm bitmaps plus a small runqueue vcpu cache so scheduler assigns short-lived IDs without global waste; implementation uses atomic bit-test/set/clear on context switch and per-runqueue cache lookups. A naive version shows ~46% hackbench overhead, but with single-thread short-circuiting and transfer-cache optimizations the measured overhead becomes negligible on perfbench; TC malloc and LTTng integrations are exercised and NUMA-affinity rules preserve node-to-ID stability.
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chapters (13)
- 0:00Introduction
- 1:08Outline and context
- 2:15Current RSEQ status
- 4:28Next steps and use cases
- 5:55Per-CPU data challenges
- 7:21Per-memory space vCPU ID extension
- 9:27Scheduler modifications
- 13:05Performance optimizations
- 18:28Benchmark results
- 27:07NUMA considerations
- 31:53NUMA-aware vCPU ID allocation
- 36:06Open questions
- 40:21Future work and Q&A
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