CXL Dynamic Capacity MM
summary
CXL 3.0 adds Dynamic Capacity Devices that present memory as fixed-size blocks grouped into 1 2 or 8 DCT regions which the host maps via CDT/HDM decoders and ACPI; drivers receive events and manage extents with DPA→HPA mapping and use mailbox commands like release_capacity. Integration plans prefer DAX-backed regions (avoid kmem pinning), must handle sparse physical holes, tagging and orchestration (including interleave across up to 16 devices), and propose emulation (ARM FVP, QEMU/KVM) to implement the simple add/remove case first, then hole punching and sharing.
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chapters (9)
- 0:00Introduction to CXL 3
- 2:48Dynamic Capacity Devices overview
- 9:32Use cases for DCd
- 11:36Questions on DCd basics
- 15:27Memory allocation and hot remove
- 17:55Virtualization and memory pooling
- 22:09Memory sharing in CXL 3
- 25:00Development and emulation plans
- 26:43Final Q&A and wrap-up
related talks
29mPlumbing challenges in Dynamic capacity device
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29mCXL HDM-DB support for Linux
43mExpanding the Memory Limits with CXL Software Stack
39mCompute Express Link(CXL), the Next Generation Interconnect - Overview and the Status of Linux
25mShared CXL 3 memory what will be required
22mKernel CXL Cache (safe) support