EPI and beyond: perspectives of a European supercomputing center on opensource hardware and software
summary
Barcelona Supercomputing Center leads RISC‑V RTL and circuit work for EPI, targeting a RISC‑V vector accelerator test chip and a compiler based on the LDM suite initially using intrinsics and supporting MPI/OpenMP. Europe approves €840M for eight new systems with €220M earmarked for the MareNostrum5 pre‑exascale node, first deployment 2021 and upgrade toward exascale 2023–24. Design targets 256‑element 64‑bit vectors and exploits the RISC‑V vector extension for microarchitecture-independent code; funding requires ~50% co‑financing and raises governance/ecosystem questions.
AI-written summary · about
chapters (16)
- 0:00Intro
- 2:53Collaborations
- 3:16Open Hardware
- 3:49New supercomputers
- 6:01New processor technologies
- 6:41HPC is important
- 7:38Europe is late
- 8:18What do we need
- 9:18Microprocessing
- 9:50Public perspective
- 10:35Roadmap
- 12:49BSC vision
- 18:24Mobile processors
- 19:32Risk v
- 24:02Approaching
- 26:23Interview
related talks
01h 01mPanel: Building a Scalable RISC-V Software Ecosystem
20mRISC-V open designs and contributions to hardware security research and development activities
18mOpen Source computer architecture research at the BSC
36mRISC-V and RISE Project BoF
20mRISC V and Chips Alliance Address new Compute Requirements
30mRISC-V: Enabling Open Physical AI
45mProcessor IP Showcase
14mRISC-V Spotlight: RISC-V: Everyone Wins
